Minimize Signal Quality Problems

Minimize Signal Quality Problems

High Speed PCB Design Guidelines – Minimize Signal Quality Problems

Strategy: Keep the instantaneous impedance the signal sees constant throughout its entire path.

  1. Use controlled impedance traces.
  2. Ideally, all signals should use the Vss or gnd planes as their return planes so there is an option of placing return vias to reduce plane resonances.
  3. When a signal transitions from one return plane to another, if it is free, add a return via in as close proximity as practical.
  4. To eliminate plane resonances, place shorting vias no farther than 1/6 a wavelength of the lowest frequency that might resonant. This is a spacing in inches ~ 1/(f in GHz)
  5. If different voltage planes are used as signal references, there should be tight coupling between the different voltage planes by keeping as thin a dielectric thickness between the layers as you can afford.
  6. If different voltage return planes, add multiple, low inductance decoupling capacitors between the different voltage planes when a signal transitions. This will be the best of bad alternatives.
  7. Use a 2D field solver to calculate the stack up design rules for the target characteristic impedance. Include the effects of solder mask and trace thickness.
  8. Use series termination for point to point topologies, either single or bidirectional if it is consistent with timing analysis.
  9. Terminate both ends of the bus in a multi-drop buss.
  10. For data rates above about 2 Gbps, only point to point routing will work.
  11. Keep the TD of stubs less than 20% the rise time of the fastest signals.
  12. Place the series terminating resistors as close to the package pads as possible.
  13. Use flyby termination for far end termination
  14. Best termination of all is on-die termination.
  15. Don’t worry about corners unless 10 fF of capacitance is important.
  16. Follow the return path of each signal and keep the width of the return path under each signal path at least as wide as the signal trace, and preferably at least 3 times as wide.
  17. Route signal traces around return path discontinuities rather than across them.
  18. Avoid using engineering change wires in any signal path.
  19. Keep all non uniform regions as short as possible.
  20. Do not use axial lead terminating resistors for system rise times less than 1 nsec. Use SMT resistors and mount them for minimum loop inductance.
  21. When rise times are less than 150 psec, do everything possible to minimize the loop inductance of the terminating SMT resistors, or consider using integrated or embedded resistors
  22. Vias generally look capacitive. Minimizing the capture pads and increasing the antipad clearance diameter will help make the via look transparent
  23. Consider adding a little capacitance to the pads of a low cost connector to compensate for its typically higher inductance.
  24. Route all differential pairs with a constant differential impedance.
  25. Avoid all asymmetries in a differential pair. Whatever you do to one trace, do the same to the other.
  26. If the spacing between the traces in a differential pair has to change, adjust the line width to keep a constant differential impedance.
  27. Add a compensation length to the short line in a differential pair in proximity to where the length asymmetry is created.
  28. It is ok to change the coupling in a differential pair as long as the differential impedance is maintained.
  29. In general, route differential pair traces with as tight a coupling as practical for highest interconnect density and lowest cost.
  30. If data rates are above 5 Gbps or long lines, consider loosely coupled to enable wider lines and lower loss.
  31. Broadside coupled differential pairs are rarely better than edge coupled. To use broadside coupled, you need a very compelling reason.
  32. For any board level differential pairs, there will be significant return current in the planes, so avoid all discontinuities in the return path. If there is a discontinuity, do exactly the same thing to each line in the pair.
  33. The only case to worry about terminating the common signals is if the common mode rejection ratio of the receiver is poor or if the reflecting common signals affect the eye quality. Terminating the common signals will not eliminate the common signal, just minimize its ringing.
  34. If losses are important, use as wide a signal trace as possible and never less than 5 mils.
  35. If losses are important, keep traces as short as possible.
  36. If losses are important, do everything possible to minimize all capacitive discontinuities.
  37. If losses are important, engineer the signal vias to look like 100 Ohms differential impedance, which usually means do everything possible to decrease the barrel size, decrease the capture pad size and increase the antipad clearance holes.
  38. Never use non-functional pads on the via pad stack.
  39. If losses are important, use as low a dissipation factor laminate as you can afford.
  40. Consider using pre-emphasis and equalization if losses are important.


Aura – Learning Platform for working professionals imparting guidance and knowledge on Electronics System Design Best Practices.

Connect with us:-