Minimize Rail Collapse

High Speed PCB Design Guidelines – Minimize Rail Collapse

Strategy: Minimize the impedance of the power distribution network.

1. Minimize the loop inductance between the power and ground paths.
2. Allocate power and ground planes on adjacent layers with as thin a dielectric as you can afford.
3. Get the lowest impedance between the planes by using as high a dielectric constant between the planes as you can afford consistent with the thinnest dielectric possible.
4. Use as many power and ground plane pairs in parallel as you can afford.
5. Route the same currents far apart and opposite currents close together.
6. Place each power via as close as practical to a ground via. If you can’t get them at least within a pitch equal to their length, there will be no coupling and no value in proximity.
7. Route the power and ground planes as close as possible to the surface where the decoupling capacitors are mounted.
8. Use multiple vias to the same power or ground pad but keep the vias as far apart as possible.
9. Use vias as large in diameter as practical when routing to power or ground planes.
10. Use double bonding on power and ground pads to minimize the loop inductance of the wire bonds.
11. Use as many power and ground connections from the chip as you can afford.
12. Use as many power and ground connections from the package as you can afford.
13. Use chip attach methods that are as short as possible, such as flip chip rather than wire bond.
14. Use package leads as short as possible, such as chip scale packages rather than QFP packages.
15. Keep all surface traces between the pads of the decoupling capacitors and their vias as short and wide as possible.
16. Use a total amount of bulk decoupling capacitance to take over from the regulator at low frequency.
17. Use a total number of decoupling capacitors to reduce the equivalent inductance at high frequency.
18. Use as small a body size decoupling capacitors as you can afford and minimize the length of all connections from the capacitor pads to the power and ground planes.
19. Place as much decoupling capacitance as you can afford on the chip itself.
20. Place as many low inductance decoupling capacitors as you can afford on the package.
21. Use differential pairs for I/Os.
22. The ONLY way of estimating the values and number of capacitors is using a simulation that includes the on-die capacitance and package lead inductance.
23. If you don’t have any information about the package or chip, select capacitors and numbers to provide a flat impedance profile from 1 MHz to about 50 MHz.

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