Board Structure/Ground Systems
1. When creating a schematic each component should have an appropriate reference designator identifying it as a member of a specific functional group. This will ensure the correct placement of components on the PCB during layout.
A recommended arrangement of functional groups on PCB is shown in Figure 1. All components should be placed with an appropriate functional group and their tracks routed within their designated PCB area.
Figure 1. Arrangement of Functional Groups on PCB
2. Place ground plane(s) under all components and all their associated tracks – a continuous ground plane with no avoidance in the IC package or I/O connector area is recommended.
3. Maximize copper areas to provide low impedance for power supply decoupling – carefully arranging components and connections (traces) may allow large areas of PCB to be filled with the ground. Figure 2
Figure 2 Maximizing Ground on PCB
4. All two-layer PCBs, where the ground plane is not feasible, should utilize a ground grid system.
The top and bottom sides of the PCB should look like a ground plane with horizontal ground tracks on one side, and vertical ground tracks on the other side. Ground grid traces should be as wide as possible and be placed apart as close as possible. A ground grid is achieved by connecting vertical and horizontal lines on opposite sides of the PCB with vias. A via is a plated through hole that interconnects two or more PCB layers. In addition, multi-layer PCBs should use ground grids even if they employ one or more ground planes. A properly designed ground grid is the next best ground system (Figure 3)
Figure 3. Ground Grid Technique
5. Install ground vias around the perimeter of the PCB every 0.5 inches or less as shown in Figure 4. Connect these vias together with 15 mils (0.4 mm) minimum trace thickness on all layers.
This should help to contain frequencies up to 5 GHz on the PCB board by forming a “Faraday’s cage”. Routing of traces outside the ground vias should not be permitted except for connections with the ‘outside world’.
Figure 4. Creating ‘Faraday’s Cage’
6. For multi-layer boards the recommended layer stack-up is shown in Figure 5
Figure 5. Layer Stack-up
7. On boards without a ground plane, i.e. two-sided boards, power, and ground traces should be routed adjacent to or on top of one another on different layers to reduce loop area (Figure 10).
8. A solid ground ‘island’ should exist underneath all High-Speed Integrated Circuits (HSICs) on surface layers. Figure 6.
9. Whenever possible, place a ground via next to all IC’s ground pins as shown in Figure 6. Frequent use of vias interconnecting grounds on both sides of the PCB or on different layers of the board may help lower RF impedance in the ground structure.
Figure 6. IC Ground
10. All ground planes, belonging to the same net, should be conductively tied together with low-impedance connections at each component’s ground pin.
11. Ground returns from high-frequency digital circuits and low-level analog circuits should never be mixed. Assure that ground return paths for analog, digital, or power signals don’t flow through each other’s circuits.
12. Keeping ground leads shorter than one-twentieth (1/20) of a wavelength may prevent excessive radiated emissions and may help to maintain low impedance.
13. Single-point grounding scheme should only be used for low-level and low-frequency circuits (below 1 MHz).
14. multi-point grounding scheme should be used for high-frequency circuits (above 1MHz) to keep ground impedance low.
15. Assure even distribution of ground pins across all connector pin fields (including ribbon cables or custom device packages) to prevent local ground upset due to transient currents. The number of connector ground pins required should be determined prior to the start of the layout.
16. There should be no floating metal of any kind near any PCB. All ground segments with a length-to-width ratio greater than 10:1 should have, at the minimum, one GND via at each end tying them to the rest of the PCB ground structure. Figure 7.
Figure 7. Eliminating Floating Ground
17. For PCBs without a ground plane, a minimum of one ground-return track should be routed adjacent to every eight lines of address and data lines to minimize the loop area. Keep the lines as short as possible. For the address lines, route the ground return next to the least significant bit (LSB) since this line is likely to be the most active.
18. Avoid ground loops. They can be the source of radiated emissions. A ground plane or ground grid is helpful in preventing ground loops from forming. Breaking a loop with a small gap may work at DC but gap capacitance may effectively close the loop at higher frequencies, creating a large loop antenna. Apart from the RE problems, large ground loops are known to cause the system to be susceptible to malfunction when subjected to external EMI sources.
19. Extend ground planes as far as possible beyond the boundaries of components and their tracks and power planes ñ ground planes should extend beyond power planes and any tracks by at least 20 times their layer spacing (Figure 8).
Figure 8. Establishing Ground Plane Boundary
Power Systems
1. Power supplies should be located close to the power entry point to PCB, and as close as possible to the powered circuitry. Closely routed tracks (to minimize the area between conductors, and hence the inductance) should be used to connect the power source to the local power distribution system.
2. Power feeds should always be decoupled at their entry points onto the PCB.
3. Bulk capacitors should always be parallel decoupled with one or smaller high-frequency capacitors with low ESL (equivalent series inductance). Place the smallest value decoupling capacitor closest to the device to be decoupled.
4. Power should be distributed with a ‘star’, grid, or power plane configuration but never with point-to-point wiring (daisy-chaining). Use the positive side of the bulk capacitor on the output of the voltage regulator as the “star” point (Figure 9).
Figure 9. Power System’s Star Point
5. The value of the bulk capacitor should be at least ten (10) times greater than the sum of all the values of decoupling capacitors.
6. High-frequency, low-inductance ceramic capacitors should be used for integrated circuit (IC) decoupling at each power pin ñ use 0.1 μF for up to 15 MHz, and 0.01 μF over 15 MHz. The decoupling capacitor should be located as close as physically possible to the IC’s power pin. Figure 6.
The power distribution system must provide sufficient current, in time, for the device to function properly. This includes high-peak current requirements during output switching. Local discrete capacitors, when placed next to the device and attached to power and ground with low inductance connections, will provide this current.
7. Printed circuit board traces which carry high switching current with fast rise/fall times (5 – 10 ns) should maintain at least 3 mm spacing from other signal traces which run parallel to them, and/or ground guard traces should be placed between them.
8. Corresponding power and ground signals should always be routed in parallel (side-by-side) or on top of each other (on adjacent layers) to minimize loop area thus reducing loop impedance (Figure 10).
Figure 10. Power and Ground Routing
9. VCC (clean power) traces should never be routed parallel to unfiltered (dirty) traces that carry the battery, ignition, high-current, or fast-switching signals.
10. Use the lowest power, slowest logic that satisfies circuit requirements.
11. Power, ground, and signal traces on the board should be kept short and as wide as possible. The traces should be shorter than the diagonal dimension of the board, and ideally, their length-to-width ratio should be kept at 10:1.
12. Placing ferrite beads on power tracks may provide attenuation of unwanted signals above 1 MHz. When properly sized, these beads can be very effective in damping high-frequency switching transients or parasitic ringing due to line reflections without causing a DC loss. CAUTION: using ferrites may impede AC current flow.
13. Devices sensing battery or ignition, such as sensing resistors, should be placed at the power entry point to PCB (close to the I/O connector).
14. Devices, such as Zener diodes, MOV, or trans zorbs should be placed at the power entry point to PCB as their function is to limit/clip transients and spikes. Assure low-impedance connection to the ground.
15. Provide enough current storage (capacitor) on the incoming battery line when designing switching power supplies and/or other circuits drawing discontinuous currents from the battery, so that these currents do not appear on the wiring harness where they can be radiated or conducted to other circuits.
16. Closely grouped Power Switching and High Current circuits should be kept separate from digital, low-level analog, and relay circuits.
17. All switching mode power supply (SMPS) traces should be routed on one layer of PCB with the SMPS reference plane placed directly on the adjacent layer to minimize the loop area.
18. Heat sink of the power-switching transistor should be connected to the same potential as the transistor’s tab, either power or ground. Sometimes the heat sink is not directly connected to the power-switching transistor but is insulated from it by a dielectric material. This produces a parasitic capacitance between the power transistor and the heat sink. Attaching the heat sink to a reference plane other than the power or ground used by the power transistor may provide a path for common-mode currents.
19. The loop area of the Switching Mode Power Supply (SMPS) Snubber circuit should be as small as physically possible (Figure 11).
20. The primary loop area of SMPS that uses a transformer should be minimized as much as possible (Figure 11). The loop includes the positive lead of the bulk capacitor, the primary windings of the transformer, the collector or drain of the switching transistor, the current sense resistor; the ground lead of the current sense resistor, and the ground lead of the bulk capacitor.
Figure 11. Primary Loop Area
21. The secondary loop area of SMPS that uses a transformer should be minimized as much as possible (Figure 12). The loop includes the positive side of the secondary windings of the transformer, the series diode, the bulk capacitor; the ground lead of the bulk capacitor, and the ground side of the secondary winding of the transformer.
Figure 12. Secondary Loop Area
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